Many computer architectures comprise one or more dedicated data storage systems handling write instructions from one or more hosts, e.g. application servers. Such hosts typically are capable of generating write instructions at a higher rate than the data storage systems are capable of handling. In order to avoid performance issues, such a data storage systems typically comprise a plurality of cache memories that receive and store the write instructions from the hosts and write these instructions to the appropriate device within the data storage system, e.g. a hard disk drive, tape or any other suitable storage device, at a later point in time. A cache management system informs the originating host that a write instruction has been completed when the received write data directed to a data storage device has been written to cache and before the write data is written out to the storage device. The write latency to the storage device is typically significantly longer than the latency to write to a cache memory. Consequentially, informing the originating host that a write instruction has been completed before the write data is written to the data storage device reduces write latency. Moreover, the presence of data in the cache memories allows for faster data access by the hosts as the data does not have to be retrieved from the data storage devices, as is of course well known per se.
It is well-documented that care has to be taken to ensure that the respective cache memories timely write, i.e. destage, the received write instructions to the respective data storage devices in order to ensure that it can still receive fresh write instructions from the hosts. It is far from trivial to meet this requirement. For instance, if a cache is allowed a high frequency of destage operations, this may keep the cache at a low occupancy level (i.e. most of the cache is empty), but this can seriously impact overall system performance, for instance because destage operations may interfere with read or other storage requests. On the other hand, if a cache is allowed a low frequency of destage operations, overall system performance can also suffer if the cache becomes full and the system is no longer able to consume write instructions in these caches, which can cause a severe increase in the latency of the system.
U.S. Pat. No. 7,394,069 B2 discloses a system for enabling and disabling cache in storage systems, including a method that changes a time period for delaying host requests received at a cache of a storage device and converts the storage device from a cache enabled state to a cache disabled state while the storage device is online. For instance, a wait time for such a request may be increased when the cache has an occupancy level of above a defined threshold to ensure that the cache is given more destaging bandwidth in order to prevent the cache from becoming full. A drawback of this approach is that performance of the system may be reduced during high workloads because caches have to handle a larger volume of write instructions, which can cause the occupancy levels of the caches to go up, consequently triggering the increase of the wait time on the host requests at a time when such wait times should be minimal.
Commonly known algorithms such as the WOW (Wise Ordering for Writes) algorithm apply a round-robin selection process for the various caches flagged as requiring to perform destage operations to give each cache access to the data storage devices at set periods in time. Caches there are not flagged as such will be overlooked. This is also far from ideal as this can cause problems in case a cache that has just been bypassed by the algorithm receives a large number of write instructions, with the cache subsequently having to wait for the round-robin algorithm to travel around all caches before considering the now overloaded cache again.